Adaptive Planning Search Algorithm for Analog Circuit Verification
- URL: http://arxiv.org/abs/2306.13484v1
- Date: Fri, 23 Jun 2023 12:57:46 GMT
- Title: Adaptive Planning Search Algorithm for Analog Circuit Verification
- Authors: Cristian Manolache, Cristina Andronache, Alexandru Caranica, Horia
Cucu, Andi Buzo, Cristian Diaconu, Georg Pelz
- Abstract summary: We propose a machine learning (ML) approach, which uses less simulations.
We show that the proposed approach is able to provide OCCs closer to the specifications for all circuits.
- Score: 53.97809573610992
- License: http://creativecommons.org/licenses/by-nc-sa/4.0/
- Abstract: Integrated circuit verification has gathered considerable interest in recent
times. Since these circuits keep growing in complexity year by year,
pre-Silicon (pre-SI) verification becomes ever more important, in order to
ensure proper functionality. Thus, in order to reduce the time needed for
manually verifying ICs, we propose a machine learning (ML) approach, which uses
less simulations. This method relies on an initial evaluation set of operating
condition configurations (OCCs), in order to train Gaussian process (GP)
surrogate models. By using surrogate models, we can propose further, more
difficult OCCs. Repeating this procedure for several iterations has shown
better GP estimation of the circuit's responses, on both synthetic and real
circuits, resulting in a better chance of finding the worst case, or even
failures, for certain circuit responses. Thus, we show that the proposed
approach is able to provide OCCs closer to the specifications for all circuits
and identify a failure (specification violation) for one of the responses of a
real circuit.
Related papers
- Quantum Error Mitigation via Linear-Depth Verifier Circuits [0.044998333629984864]
We provide a method for constructing verifier circuits for any quantum circuit that is accurately represented by a low-dimensional matrix product operator (MPO)
By transpiling the circuits to a 2D array of qubits, we estimate the crossover point where the verifier circuit is shallower than the circuit itself, and hence useful for quantum error mitigation (QEM)
We conclude that our approach may be useful for calibrating quantum sub-circuits to counter coherent noise but cannot correct for the incoherent noise present in current devices.
arXiv Detail & Related papers (2024-11-05T16:44:18Z) - CktGen: Specification-Conditioned Analog Circuit Generation [28.780603785886242]
We introduce a task that directly generates analog circuits based on specified specifications.
Specifically, we propose CktGen, a simple yet effective variational autoencoder (VAE) model.
We conduct comprehensive experiments on the Open Circuit Benchmark (OCB) and introduce new evaluation metrics for cross-model consistency.
arXiv Detail & Related papers (2024-10-01T18:35:44Z) - Adversarial Circuit Evaluation [1.1893676124374688]
We evaluate three circuits found in the literature (IOI, greater-than, and docstring) in an adversarial manner.
We measure the KL divergence between the full model's output and the circuit's output, calculated through resample ablation, and we analyze the worst-performing inputs.
arXiv Detail & Related papers (2024-07-21T13:43:44Z) - LaMAGIC: Language-Model-based Topology Generation for Analog Integrated Circuits [17.002169206594793]
We introduce LaMAGIC, a pioneering language model-based topology generation model.
LaMAGIC can efficiently generate an optimized circuit design from the custom specification in a single pass.
LaMAGIC achieves a success rate of up to 96% under a strict tolerance of 0.01.
arXiv Detail & Related papers (2024-07-19T22:51:41Z) - Finding Transformer Circuits with Edge Pruning [71.12127707678961]
We propose Edge Pruning as an effective and scalable solution to automated circuit discovery.
Our method finds circuits in GPT-2 that use less than half the number of edges compared to circuits found by previous methods.
Thanks to its efficiency, we scale Edge Pruning to CodeLlama-13B, a model over 100x the scale that prior methods operate on.
arXiv Detail & Related papers (2024-06-24T16:40:54Z) - Fault-tolerant quantum architectures based on erasure qubits [49.227671756557946]
We exploit the idea of erasure qubits, relying on an efficient conversion of the dominant noise into erasures at known locations.
We propose and optimize QEC schemes based on erasure qubits and the recently-introduced Floquet codes.
Our results demonstrate that, despite being slightly more complex, QEC schemes based on erasure qubits can significantly outperform standard approaches.
arXiv Detail & Related papers (2023-12-21T17:40:18Z) - Model-based Deep Learning Receiver Design for Rate-Splitting Multiple
Access [65.21117658030235]
This work proposes a novel design for a practical RSMA receiver based on model-based deep learning (MBDL) methods.
The MBDL receiver is evaluated in terms of uncoded Symbol Error Rate (SER), throughput performance through Link-Level Simulations (LLS) and average training overhead.
Results reveal that the MBDL outperforms by a significant margin the SIC receiver with imperfect CSIR.
arXiv Detail & Related papers (2022-05-02T12:23:55Z) - Domain Knowledge-Infused Deep Learning for Automated
Analog/Radio-Frequency Circuit Parameter Optimization [6.599793419469274]
This paper presents a reinforcement learning method to automate the analog circuit parameter optimization.
It is inspired by human experts who rely on domain knowledge of analog circuit design.
Experimental results on exemplary circuits show it achieves human-level design accuracy (99%) 1.5X efficiency of existing best-performing methods.
arXiv Detail & Related papers (2022-04-27T13:58:51Z) - Quantum circuit debugging and sensitivity analysis via local inversions [62.997667081978825]
We present a technique that pinpoints the sections of a quantum circuit that affect the circuit output the most.
We demonstrate the practicality and efficacy of the proposed technique by applying it to example algorithmic circuits implemented on IBM quantum machines.
arXiv Detail & Related papers (2022-04-12T19:39:31Z) - Combining Deep Learning and Optimization for Security-Constrained
Optimal Power Flow [94.24763814458686]
Security-constrained optimal power flow (SCOPF) is fundamental in power systems.
Modeling of APR within the SCOPF problem results in complex large-scale mixed-integer programs.
This paper proposes a novel approach that combines deep learning and robust optimization techniques.
arXiv Detail & Related papers (2020-07-14T12:38:21Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.