Low-latency machine learning FPGA accelerator for multi-qubit state discrimination

• URL: http://arxiv.org/abs/2407.03852v1
• Date: Thu, 4 Jul 2024 11:34:43 GMT
• Title: Low-latency machine learning FPGA accelerator for multi-qubit state discrimination
• Authors: Pradeep Kumar Gautam, Shantharam Kalipatnapu, Shankaranarayanan H, Ujjawal Singhal, Benjamin Lienhard, Vibhor Singh, Chetan Singh Thakur,
• Abstract summary: In this work, we utilize an integrated approach to deploy neural networks (NN) on to field programmable gate arrays (FPGA) We demonstrate that it is practical to design and implement a fully connected neural network accelerator for frequency-multiplexed readout. The hardware accelerator performs frequency-multiplexed readout of 5 superconducting qubits in less than 50 ns on RFSoC ZCU111 FPGA.
• Score: 1.6773398825542363
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Measuring a qubit is a fundamental yet error prone operation in quantum computing. These errors can stem from various sources such as crosstalk, spontaneous state-transitions, and excitation caused by the readout pulse. In this work, we utilize an integrated approach to deploy neural networks (NN) on to field programmable gate arrays (FPGA). We demonstrate that it is practical to design and implement a fully connected neural network accelerator for frequency-multiplexed readout balancing computational complexity with low latency requirements without significant loss in accuracy. The neural network is implemented by quantization of weights, activation functions, and inputs. The hardware accelerator performs frequency-multiplexed readout of 5 superconducting qubits in less than 50 ns on RFSoC ZCU111 FPGA which is first of its kind in the literature. These modules can be implemented and integrated in existing Quantum control and readout platforms using a RFSoC ZCU111 ready for experimental deployment.

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