Logical Maneuvers: Detecting and Mitigating Adversarial Hardware Faults in Space
- URL: http://arxiv.org/abs/2501.13894v2
- Date: Mon, 10 Feb 2025 17:15:49 GMT
- Title: Logical Maneuvers: Detecting and Mitigating Adversarial Hardware Faults in Space
- Authors: Fatemeh Khojasteh Dana, Saleh Khalaj Monfared, Shahin Tajik,
- Abstract summary: Satellites are vulnerable to adversarial glitches or high-energy radiation in space, which could cause faults on the onboard computer.<n>This work introduces a detection- and response-based countermeasure to deal with partially damaged processor chips.<n>We incorporate digitally-compatible delay-based sensors on the target processor's chip to reliably detect the incoming radiation.
- Score: 3.766999700958066
- License: http://creativecommons.org/licenses/by-nc-sa/4.0/
- Abstract: Satellites are highly vulnerable to adversarial glitches or high-energy radiation in space, which could cause faults on the onboard computer. Various radiation- and fault-tolerant methods, such as error correction codes (ECC) and redundancy-based approaches, have been explored over the last decades to mitigate temporary soft errors on software and hardware. However, conventional ECC methods fail to deal with hard errors or permanent faults in the hardware components. This work introduces a detection- and response-based countermeasure to deal with partially damaged processor chips. It recovers the processor chip from permanent faults and enables continuous operation with available undamaged resources on the chip. We incorporate digitally-compatible delay-based sensors on the target processor's chip to reliably detect the incoming radiation or glitching attempts on the physical fabric of the chip, even before a fault occurs. Upon detecting a fault in one or more components of the processor's arithmetic logic unit (ALU), our countermeasure employs adaptive software recompilations to resynthesize and substitute the affected instructions with instructions of still functioning components to accomplish the task. Furthermore, if the fault is more widespread and prevents the correct operation of the entire processor, our approach deploys adaptive hardware partial reconfigurations to replace and reroute the failed components to undamaged locations of the chip. To validate our claims, we deploy a high-energy near-infrared (NIR) laser beam on a RISC-V processor implemented on a 28~nm FPGA to emulate radiation and even hard errors by partially damaging the FPGA fabric. We demonstrate that our sensor can confidently detect the radiation and trigger the processor testing and fault recovery mechanisms. Finally, we discuss the overhead imposed by our countermeasure.
Related papers
- Lightweight Fault Detection Architecture for NTT on FPGA [0.8793721044482612]
Post-Quantum Cryptographic (PQC) algorithms are mathematically secure and resistant to quantum attacks.<n>They can still leak sensitive information in hardware implementations due to natural faults or intentional fault injections.<n>This research proposes a lightweight, efficient, recomputation-based fault detection module.
arXiv Detail & Related papers (2025-08-05T04:23:50Z) - Detecting Hardware Trojans in Microprocessors via Hardware Error Correction Code-based Modules [49.1574468325115]
Hardware Trojans (HTs) enable attackers to execute unauthorized software or gain illicit access to privileged operations.<n>This manuscript introduces a hardware-based methodology for detecting runtime HT activations using Error Correction Codes (ECCs) on a RISC-V microprocessor.
arXiv Detail & Related papers (2025-06-18T12:37:14Z) - Fooling the Decoder: An Adversarial Attack on Quantum Error Correction [49.48516314472825]
In this work, we target a basic RL surface code decoder (DeepQ) to create the first adversarial attack on quantum error correction.
We demonstrate an attack that reduces the logical qubit lifetime in memory experiments by up to five orders of magnitude.
This attack highlights the susceptibility of machine learning-based QEC and underscores the importance of further research into robust QEC methods.
arXiv Detail & Related papers (2025-04-28T10:10:05Z) - Leveraging Atom Loss Errors in Fault Tolerant Quantum Algorithms [0.0]
Errors associated with qubit loss constitute an important source of noise in many quantum hardware systems.
We develop a theoretical framework to handle these errors in logical algorithms, incorporating decoding techniques and circuit-level optimizations.
We simulate such a teleportation-based algorithm, involving a toy model for small-angle synthesis and find a significant improvement in logical error rates as the loss fraction increases.
arXiv Detail & Related papers (2025-02-27T21:59:25Z) - Real-Time Multi-Modal Subcomponent-Level Measurements for Trustworthy System Monitoring and Malware Detection [20.93359969847573]
Modern computers are complex systems with multiple interacting subcomponents.<n>We propose a "subcomponent-level" approach to collect side channel measurements.<n>By enabling real-time measurements from multiple subcomponents, the goal is to provide a deeper visibility into system operation.
arXiv Detail & Related papers (2025-01-22T18:44:00Z) - Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults [9.89051364546275]
We propose novel approaches that quantify permanent hardware faults in neural network (NN) accelerators by uniquely integrating the behavior of the faulty component instead of bypassing it.<n>We propose several algorithmic mitigation techniques for a subset of stuck-at faults, such as Invertible Scaling or Shifting of activations and weights, or fine tuning with the faulty behavior.<n> Notably, the proposed techniques do not require any hardware modification, instead relying on existing components of widely used systolic array based accelerators.
arXiv Detail & Related papers (2024-12-17T18:56:09Z) - Accelerating Error Correction Code Transformers [56.75773430667148]
We introduce a novel acceleration method for transformer-based decoders.
We achieve a 90% compression ratio and reduce arithmetic operation energy consumption by at least 224 times on modern hardware.
arXiv Detail & Related papers (2024-10-08T11:07:55Z) - On the Efficacy of Surface Codes in Compensating for Radiation Events in Superconducting Devices [2.1204495827342438]
We report data from over 400 million fault injections and correlate hardware faults with the logical error observed after decoding the code output.
We show that, by simply selecting and tuning properly the surface code, the probability of correcting a radiation-induced fault is increased by up to 10%.
arXiv Detail & Related papers (2024-07-15T15:56:09Z) - Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
We develop a reinforcement learning-based quantum compiler for a superconducting processor.
We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths.
Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
arXiv Detail & Related papers (2024-06-18T01:49:48Z) - A Micro Architectural Events Aware Real-Time Embedded System Fault Injector [0.12187048691454236]
This paper introduces a novel fault injector designed to facilitate the monitoring, aggregation, and examination of micro-architectural events.
The methodology targets bit-flipping within the memory system, affecting CPU registers and RAM.
The outcomes of these fault injections enable a thorough analysis of the impact of soft errors and establish a robust correlation between the identified faults and the essential timing predictability demanded by SACRES.
arXiv Detail & Related papers (2024-01-16T14:41:20Z) - Deep Quantum Error Correction [73.54643419792453]
Quantum error correction codes (QECC) are a key component for realizing the potential of quantum computing.
In this work, we efficiently train novel emphend-to-end deep quantum error decoders.
The proposed method demonstrates the power of neural decoders for QECC by achieving state-of-the-art accuracy.
arXiv Detail & Related papers (2023-01-27T08:16:26Z) - Fault-tolerant parity readout on a shuttling-based trapped-ion quantum
computer [64.47265213752996]
We experimentally demonstrate a fault-tolerant weight-4 parity check measurement scheme.
We achieve a flag-conditioned parity measurement single-shot fidelity of 93.2(2)%.
The scheme is an essential building block in a broad class of stabilizer quantum error correction protocols.
arXiv Detail & Related papers (2021-07-13T20:08:04Z) - Towards Online Monitoring and Data-driven Control: A Study of
Segmentation Algorithms for Laser Powder Bed Fusion Processes [83.97264034062673]
An increasing number of laser powder bed fusion machines use off-axis infrared cameras to improve online monitoring and data-driven control capabilities.
We study over 30 segmentation algorithms that segment each infrared image into a foreground and background.
The identified algorithms can be readily applied to the laser powder bed fusion machines to address each of the above limitations and thus, significantly improve process control.
arXiv Detail & Related papers (2020-11-18T03:30:16Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.