Real-Time Cell Sorting with Scalable In Situ FPGA-Accelerated Deep Learning

• URL: http://arxiv.org/abs/2503.12622v2
• Date: Wed, 22 Oct 2025 18:46:31 GMT
• Title: Real-Time Cell Sorting with Scalable In Situ FPGA-Accelerated Deep Learning
• Authors: Khayrul Islam, Ryan F. Forelli, Jianzhong Han, Deven Bhadane, Jian Huang, Joshua C. Agar, Nhan Tran, Seda Ogrenci, Yaling Liu,
• Abstract summary: We present a label-free machine learning framework for cell classification using bright-field microscopy images.<n>Our framework accurately classifies T4, T8, and B cell types with a dataset of 80,000 preprocessed images.<n>Our FPGA-accelerated student model achieves an ultra-low latency of just 14.5$mu$s and a complete cell detection-to-sorting trigger time of 24.7$mu$s.
• Score: 2.0717688648414065
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Precise cell classification is essential in biomedical diagnostics and therapeutic monitoring, particularly for identifying diverse cell types involved in various diseases. Traditional cell classification methods such as flow cytometry depend on molecular labeling which is often costly, time-intensive, and can alter cell integrity. To overcome these limitations, we present a label-free machine learning framework for cell classification, designed for real-time sorting applications using bright-field microscopy images. This approach leverages a teacher-student model architecture enhanced by knowledge distillation, achieving high efficiency and scalability across different cell types. Demonstrated through a use case of classifying lymphocyte subsets, our framework accurately classifies T4, T8, and B cell types with a dataset of 80,000 preprocessed images, accessible via an open-source Python package for easy adaptation. Our teacher model attained 98\% accuracy in differentiating T4 cells from B cells and 93\% accuracy in zero-shot classification between T8 and B cells. Remarkably, our student model operates with only 0.02\% of the teacher model's parameters, enabling field-programmable gate array (FPGA) deployment. Our FPGA-accelerated student model achieves an ultra-low inference latency of just 14.5~$\mu$s and a complete cell detection-to-sorting trigger time of 24.7~$\mu$s, delivering 12x and 40x improvements over the previous state-of-the-art real-time cell analysis algorithm in inference and total latency, respectively, while preserving accuracy comparable to the teacher model. This framework provides a scalable, cost-effective solution for lymphocyte classification, as well as a new SOTA real-time cell sorting implementation for rapid identification of subsets using in situ deep learning on off-the-shelf computing hardware.

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