Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication

• URL: http://arxiv.org/abs/2509.00778v1
• Date: Sun, 31 Aug 2025 10:15:35 GMT
• Title: Energy Efficient Exact and Approximate Systolic Array Architecture for Matrix Multiplication
• Authors: Pragun Jaswal, L. Hemanth Krishna, B. Srinivasu,
• Abstract summary: Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations.<n>This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs)<n>The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively.
• Score: 0.0
• License: http://creativecommons.org/publicdomain/zero/1.0/
• Abstract: Deep Neural Networks (DNNs) require highly efficient matrix multiplication engines for complex computations. This paper presents a systolic array architecture incorporating novel exact and approximate processing elements (PEs), designed using energy-efficient positive partial product and negative partial product cells, termed as PPC and NPPC, respectively. The proposed 8-bit exact and approximate PE designs are employed in a 8x8 systolic array, which achieves a energy savings of 22% and 32%, respectively, compared to the existing design. To demonstrate their effectiveness, the proposed PEs are integrated into a systolic array (SA) for Discrete Cosine Transform (DCT) computation, achieving high output quality with a PSNR of 38.21,dB. Furthermore, in an edge detection application using convolution, the approximate PE achieves a PSNR of 30.45,dB. These results highlight the potential of the proposed design to deliver significant energy efficiency while maintaining competitive output quality, making it well-suited for error-resilient image and vision processing applications.

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