COMPAS: A Distributed Multi-Party SWAP Test for Parallel Quantum Algorithms

• URL: http://arxiv.org/abs/2511.23434v1
• Date: Fri, 28 Nov 2025 18:31:15 GMT
• Title: COMPAS: A Distributed Multi-Party SWAP Test for Parallel Quantum Algorithms
• Authors: Brayden Goldstein-Gelb, Kun Liu, John M. Martyn, Hengyun Zhou, Yongshan Ding, Yuan Liu,
• Abstract summary: We introduce COMPAS, an architecture that realizes multivariate trace estimation across a multi-party network of interconnected modular and distributed QPUs.<n>Unlike other schemes, which must choose between optimality in circuit depth or GHZ width, COMPAS achieves both at once.<n>We analyze network-level errors and simulate the effects of circuit-level noise on the architecture.
• Score: 4.584616394519209
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The limited number of qubits per chip remains a critical bottleneck in quantum computing, motivating the use of distributed architectures that interconnect multiple quantum processing units (QPUs). However, executing quantum algorithms across distributed systems requires careful co-design of algorithmic primitives and hardware architectures to manage circuit depth and entanglement overhead. We identify multivariate trace estimation as a key subroutine that is naturally suited for distribution, and broadly useful in tasks such as estimating Rényi entropies, virtual cooling and distillation, and certain applications of quantum signal processing. In this work, we introduce COMPAS, an architecture that realizes multivariate trace estimation across a multi-party network of interconnected modular and distributed QPUs by leveraging pre-shared entangled Bell pairs as resources. COMPAS adds only a constant depth overhead and consumes Bell pairs at a rate linear in circuit width, making it suitable for near-term hardware. Unlike other schemes, which must choose between asymptotic optimality in circuit depth or GHZ width, COMPAS achieves both at once. Additionally, we analyze network-level errors and simulate the effects of circuit-level noise on the architecture.

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