Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design

• URL: http://arxiv.org/abs/2602.20521v1
• Date: Tue, 24 Feb 2026 03:49:12 GMT
• Title: Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design
• Authors: Wei Xuan, Zihao Xuan, Rongliang Fu, Ning Lin, Kwunhang Wong, Zikang Yuan, Lang Feng, Zhongrui Wang, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang,
• Abstract summary: This paper presents a secure and efficient memory protection framework for deep neural network (DNN) accelerators with minimal overhead.<n>First, we propose a bandwidth-aware cryptographic scheme that adapts encryption granularity based on memory traffic patterns.<n>Second, we observe that both the overlapping regions in the intra-layer's sliding window pattern and those resulting from inter-layer tiling strategy discrepancies introduce substantial redundant memory accesses.<n>Third, we introduce a multi-level authentication mechanism that effectively eliminates unnecessary off-chip memory accesses, enhancing performance and energy efficiency.
• Score: 18.80243704372307
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: The rapid deployment of deep neural network (DNN) accelerators in safety-critical domains such as autonomous vehicles, healthcare systems, and financial infrastructure necessitates robust mechanisms to safeguard data confidentiality and computational integrity. Existing security solutions for DNN accelerators, however, suffer from excessive hardware resource demands and frequent off-chip memory access overheads, which degrade performance and scalability. To address these challenges, this paper presents a secure and efficient memory protection framework for DNN accelerators with minimal overhead. First, we propose a bandwidth-aware cryptographic scheme that adapts encryption granularity based on memory traffic patterns, striking a balance between security and resource efficiency. Second, we observe that both the overlapping regions in the intra-layer tiling's sliding window pattern and those resulting from inter-layer tiling strategy discrepancies introduce substantial redundant memory accesses and repeated computational overhead in cryptography. Third, we introduce a multi-level authentication mechanism that effectively eliminates unnecessary off-chip memory accesses, enhancing performance and energy efficiency. Experimental results show that this work decreases performance overhead by over 12% and achieves 87% energy efficiency improvement for both server and edge neural processing units (NPUs), while ensuring robust scalability.

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