Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures
- URL: http://arxiv.org/abs/2603.16389v3
- Date: Wed, 25 Mar 2026 09:19:49 GMT
- Title: Chipmunq: A Fault-Tolerant Compiler for Chiplet Quantum Architectures
- Abstract summary: We present Chipmunq, the first hardware-aware compiler for mapping and routing fault-tolerant circuits onto modular architectures.<n>Chipmunq achieves a 13.5x speedup in compilation time compared to state-of-the-art tools.
- Score: 40.10865338207471
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: As quantum computing advances toward fault-tolerance through quantum error correction, modular chiplet architectures have emerged to provide the massive qubit counts required while overcoming fabrication limits of monolithic chips. However, this transition introduces a critical compilation gap: existing frameworks cannot handle the scale of fault-tolerant quantum circuits while managing the noisy, sparse interconnects of chiplet backends. We present Chipmunq, the first hardware-aware compiler for mapping and routing fault-tolerant circuits onto modular architectures. Chipmunq employs a quantum-error-correction-aware partitioning strategy that preserves the integrity of logical qubit patches, preventing prohibitive gate overheads common in general-purpose compilers. Our evaluation demonstrates that Chipmunq achieves a 13.5x speedup in compilation time compared to state-of-the-art tools. By incorporating chiplet constraints and defective qubits, it reduces circuit depth by 86.4% and SWAP gate counts by 91.4% across varying code distances. Crucially, Chipmunq overcomes heterogeneous inter-chiplet links, improving logical error rates by up to two orders of magnitude.
Related papers
- Hardware-aware Compilation for Chip-to-Chip Coupler-Connected Modular Quantum Systems [7.509466019910955]
We introduce CCMap, a circuit-compiler co-design framework that enhances existing quantum compilers with system-level coordination across modular chips.<n>Results show that CCMap improves circuit fidelity by up to 21.9%, representing a 30% increase, and reduces compilation cost by up to 58.6% over state-of-the-art baselines.
arXiv Detail & Related papers (2025-05-14T00:20:56Z) - Performance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers [63.42120407991982]
Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors.<n>We present a design for a multi-chip module comprising one carrier chip and four qubit modules.<n>Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 times 10-3$ in 200 ns.<n>We demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 times 10-3$ extracted from interleaved randomized benchmarking.
arXiv Detail & Related papers (2025-03-16T18:32:44Z) - Modular Compilation for Quantum Chiplet Architectures [0.8169527563677724]
Complexity of chiplet-based quantum devices, coupled with their growing size, presents an imminent scalability challenge for quantum compilation.<n>We propose SEQC, a hierarchical parallelized compilation pipeline optimized for chiplet-based quantum systems.
arXiv Detail & Related papers (2025-01-14T22:41:29Z) - Hardware-aware Circuit Cutting and Distributed Qubit Mapping for Connected Quantum Systems [23.861374790490576]
DisMap is a self-adaptive, hardware-aware framework for chip-to-chip distributed quantum systems.<n>It analyzes qubit noise and error rates to construct a virtual system topology, guiding circuit partitioning, and distributed qubit mapping.<n>DisMap achieves up to a 20.8% improvement in fidelity and reduces SWAP overhead by as much as 80.2%.
arXiv Detail & Related papers (2024-12-24T14:32:06Z) - Tackling Coherent Noise in Quantum Computing via Cross-Layer Compiler Optimization [1.6436891312063917]
Quantum computing hardware is affected by quantum noise that undermine the quality of results of an executed quantum program.
Coherent error that caused by parameter drifting and miscalibration remains critical.
This work proposes a cross-layer approach for coherent error mitigation.
arXiv Detail & Related papers (2024-10-12T22:39:06Z) - Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
We develop a reinforcement learning-based quantum compiler for a superconducting processor.
We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths.
Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
arXiv Detail & Related papers (2024-06-18T01:49:48Z) - Fault-tolerant quantum architectures based on erasure qubits [49.227671756557946]
We exploit the idea of erasure qubits, relying on an efficient conversion of the dominant noise into erasures at known locations.
We propose and optimize QEC schemes based on erasure qubits and the recently-introduced Floquet codes.
Our results demonstrate that, despite being slightly more complex, QEC schemes based on erasure qubits can significantly outperform standard approaches.
arXiv Detail & Related papers (2023-12-21T17:40:18Z) - Optimizing quantum gates towards the scale of logical qubits [78.55133994211627]
A foundational assumption of quantum gates theory is that quantum gates can be scaled to large processors without exceeding the error-threshold for fault tolerance.
Here we report on a strategy that can overcome such problems.
We demonstrate it by choreographing the frequency trajectories of 68 frequency-tunablebits to execute single qubit while superconducting errors.
arXiv Detail & Related papers (2023-08-04T13:39:46Z) - Modular decoding: parallelizable real-time decoding for quantum
computers [55.41644538483948]
Real-time quantum computation will require decoding algorithms capable of extracting logical outcomes from a stream of data generated by noisy quantum hardware.
We propose modular decoding, an approach capable of addressing this challenge with minimal additional communication and without sacrificing decoding accuracy.
We introduce the edge-vertex decomposition, a concrete instance of modular decoding for lattice-surgery style fault-tolerant blocks.
arXiv Detail & Related papers (2023-03-08T19:26:10Z) - Scaling Superconducting Quantum Computers with Chiplet Architectures [4.8041390724795585]
Fixed-frequency transmon quantum computers (QCs) have advanced in coherence times, addressability, and gate fidelities.
QCs are restricted by the number of on-chip qubits, capping processing power and slowing progress toward fault-tolerance.
We propose exploiting the higher yields associated with smaller QCs by integrating quantum chiplets within quantum multi-chip modules.
arXiv Detail & Related papers (2022-10-19T22:56:59Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.