Suppression of Universal Errors in DFS-Encoded Superconducting Geometric Logical \emph{T} Gate

• URL: http://arxiv.org/abs/2605.00552v1
• Date: Fri, 01 May 2026 10:27:08 GMT
• Title: Suppression of Universal Errors in DFS-Encoded Superconducting Geometric Logical \emph{T} Gate
• Abstract summary: We propose a controlled superconducting geometric logical emphT gate scheme that achieves high-order suppression of universal errors.<n> Numerical simulations reveal that, within tunable superconducting quantum circuits, our geometric logical emphT gate outperforms both conventional composite geometric and dynamical gates.
• Score: 25.998584933763862
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: High-fidelity logical \emph{T}-gate realization constitutes a core prerequisite for large-scale fault-tolerant quantum computing. However, conventional magic state distillation requires massive physical qubit overhead across successive distillation rounds, alongside sophisticated measurement and feedback control, thereby inducing considerable spatial and temporal resource consumption. Herein, we propose a controlled superconducting geometric logical \emph{T} gate scheme that achieves high-order suppression of universal errors, by integrating decoherence-free subspace encoding with multi-loop optimized composite geometric pulse engineering. Guided by tailored trajectory design, we systematically establish unified gate construction frameworks for conventional geometric, composite geometric, and optimized composite geometric protocols. By flexibly controling additional parametric degrees of freedom, the proposed scheme achieves substantially enhanced robustness against diverse noise sources. Numerical simulations reveal that, within tunable superconducting quantum circuits, our geometric logical \emph{T} gate outperforms both conventional composite geometric and dynamical gates in suppressing Rabi frequency, detuning, and residual inter-qubit crosstalk errors that can all be suppressed to the fourth order, while additionally providing inherent suppression of collective dephasing errors. The present strategy alleviates intrinsic limitations of mainstream approaches and opens a promising avenue toward robust high-fidelity logical \emph{T} gate construction.

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