Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs

• URL: http://arxiv.org/abs/2605.07417v1
• Date: Fri, 08 May 2026 08:11:15 GMT
• Title: Effective and Memory-Efficient Alternatives to ECC for Reliable Large-Scale DNNs
• Abstract summary: We propose two lightweight alternatives to Error Correction Codes (ECCs) that achieve superior reliability.<n>The first approach, MSET, selectively hardens the most vulnerable bits in CNN and ViT parameters.<n>The second approach, CEP, provides fine-grained protection for all parameter bits.
• Score: 0.20524609401792393
• License: http://creativecommons.org/licenses/by-nc-nd/4.0/
• Abstract: Modern Deep Learning (DL) workloads are increasingly deployed in safety-critical domains, such as automotive systems and hyperscale data centers, where transient hardware faults pose a serious threat to system reliability. These workloads are highly memory-intensive, and their correct functionality strongly depends on model parameters stored in memory, which are typically protected using Error Correction Codes (ECCs). In this work, we study ECC's impact on such models and propose two lightweight alternatives to ECCs that achieve superior reliability. The first approach, MSET, selectively hardens the most vulnerable bits in CNN and ViT parameters, while the second approach, CEP, provides fine-grained protection for all parameter bits. Experimental results demonstrate that both methods significantly enhance the reliability of large CNNs and ViTs, mostly outperforming conventional Single Error Detection Double Error Correction (SECDED) ECC schemes, with no memory overhead and, in fact, with considerably lower area and delay characteristics when compared to SECDEC. Experimental results indicate that ViTs can be effectively protected by merely protecting their highest exponent bits in FP16 and FP32 representations. Furthermore, applying the CEP technique can guarantee the resilience of DNNs by up to one order of magnitude higher BERs, with a 3.5x lower area overhead and 7x faster decoder compared to SECDED ECC.

Related papers

• MESA: Improving MoE Safety Alignment via Decentralized Expertise [55.297863000560596]
  MESA (MoE Safety Alignment) is a targeted alignment framework for MoE-based Large Language Models.<n>It strategically decentralizes safety responsibility to maximize coverage while minimizing interference with utility.<n>MESA achieves robust defensive performance against varied harmful benchmarks while preserving helpfulness.
  arXiv  Detail & Related papers  (2026-05-30T09:54:38Z)
• Efficient Adversarial Training via Criticality-Aware Fine-Tuning [59.84340722595335]
  Criticality-Aware Adversarial Training (CAAT) is a novel method that adaptively allocates resources to the most robustness-critical parameters.<n>CAAT incurs only a 4.3% decrease in adversarial robustness while tuning approximately 6% of its parameters.<n>Experiments on three widely used adversarial learning datasets demonstrate that CAAT outperforms state-of-the-art lightweight AT methods with fewer trainable parameters.
  arXiv  Detail & Related papers  (2026-04-14T14:17:38Z)
• Taming the Instability: A Robust Second-Order Optimizer for Federated Learning over Non-IID Data [77.19117648492104]
  We present Federated Robust Curvature Optimization (FedRCO), a novel second-order optimization framework designed to improve convergence speed and reduce communication cost.<n>FedRCO addresses these challenges by integrating an efficient approximate curvature with a provable stability mechanism.<n>We show that FedRCO achieves superior robustness against diverse non-IID scenarios while achieving higher accuracy and faster convergence than both state-of-the-art first-order and second-order methods.
  arXiv  Detail & Related papers  (2026-03-30T11:37:46Z)
• When Small Variations Become Big Failures: Reliability Challenges in Compute-in-Memory Neural Accelerators [10.520875052654771]
  We show that even small device variations can lead to disproportionately high accuracy degradation and catastrophic failures in safety-critical inference workloads.<n>We introduce SWIM, a selective write-verify mechanism that strategically applies verification only where it is most impactful.<n>Finally, we explore a learning-centric solution that improves realistic worst-case performance by training networks with right-censored noise.
  arXiv  Detail & Related papers  (2026-03-03T20:08:25Z)
• Towards Secure and Efficient DNN Accelerators via Hardware-Software Co-Design [18.80243704372307]
  This paper presents a secure and efficient memory protection framework for deep neural network (DNN) accelerators with minimal overhead.<n>First, we propose a bandwidth-aware cryptographic scheme that adapts encryption granularity based on memory traffic patterns.<n>Second, we observe that both the overlapping regions in the intra-layer's sliding window pattern and those resulting from inter-layer tiling strategy discrepancies introduce substantial redundant memory accesses.<n>Third, we introduce a multi-level authentication mechanism that effectively eliminates unnecessary off-chip memory accesses, enhancing performance and energy efficiency.
  arXiv  Detail & Related papers  (2026-02-24T03:49:12Z)
• Secure Code Generation via Online Reinforcement Learning with Vulnerability Reward Model [60.60587869092729]
  Large language models (LLMs) are increasingly used in software development, yet their tendency to generate insecure code remains a major barrier to real-world deployment.<n>We propose SecCoderX, an online reinforcement learning framework for functionality-preserving secure code generation.
  arXiv  Detail & Related papers  (2026-02-07T07:42:07Z)
• Large-Scale Model Enabled Semantic Communication Based on Robust Knowledge Distillation [45.347078403677216]
  Large-scale models (LSMs) can be an effective framework for semantic representation and understanding.<n>However, their direct deployment is often hindered by high computational complexity and resource requirements.<n>This paper proposes a novel knowledge distillation based semantic communication framework.
  arXiv  Detail & Related papers  (2025-08-04T07:47:18Z)
• Securing Transformer-based AI Execution via Unified TEEs and Crypto-protected Accelerators [19.93096649006403]
  Machine learning runs on untrusted cloud infrastructure, exposing data and models to potential breaches.<n>Running model inference entirely within trusted execution environments (TEEs) is subject to non-trivial slowdown.<n>We propose TwinShield, a framework enabling secure Transformer inference in heterogeneous TEE and accelerator systems.
  arXiv  Detail & Related papers  (2025-07-04T03:52:53Z)
• Overlapping Error Correction Codes on Two-Dimensional Structures [0.0]
  This work proposes a technique to enhance Error Correction Codes (ECCs) by overlapping data regions.<n>The approach consists of protecting the same data area with multiple ECCs organized in a two-dimensional structure.<n>Different configurations of overlapping ECCs were analyzed to evaluate the proposal regarding error detection and correction capability, scalability, and reliability.
  arXiv  Detail & Related papers  (2025-04-16T14:53:12Z)
• FT-Transformer: Resilient and Reliable Transformer with End-to-End Fault Tolerant Attention [5.261954615957387]
  Existing fault tolerance frameworks for Transformers are designed at the operation level without architectural optimization.<n>In this paper, we implement module-level protection for Transformers by treating the operations within the attention module as a single kernel.<n>We show that our end-to-end fault tolerance achieves up to 7.56x speedup over traditional methods with an average fault tolerance overhead of 13.9%.
  arXiv  Detail & Related papers  (2025-04-03T02:05:08Z)
• Digital Twin-Assisted Data-Driven Optimization for Reliable Edge Caching in Wireless Networks [60.54852710216738]
  We introduce a novel digital twin-assisted optimization framework, called D-REC, to ensure reliable caching in nextG wireless networks. By incorporating reliability modules into a constrained decision process, D-REC can adaptively adjust actions, rewards, and states to comply with advantageous constraints.
  arXiv  Detail & Related papers  (2024-06-29T02:40:28Z)
• Practical Conformer: Optimizing size, speed and flops of Conformer for on-Device and cloud ASR [67.63332492134332]
  We design an optimized conformer that is small enough to meet on-device restrictions and has fast inference on TPUs. Our proposed encoder can double as a strong standalone encoder in on device, and as the first part of a high-performance ASR pipeline.
  arXiv  Detail & Related papers  (2023-03-31T23:30:48Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.