DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity

• URL: http://arxiv.org/abs/2609.09254v1
• Date: Tue, 08 Sep 2026 15:00:50 GMT
• Title: DiffLUT-Net: Differentiable Training of FPGA LUT Networks with Learnable Connectivity
• Abstract summary: We present DiffLUT-Net, an FPGA-native network connected by six-input LUTs that are trained from scratch.<n>After training, the truth tables and connections are discretized, unused logic can be pruned, and the network is exported directly as Verilog.
• Score: 7.054660214035757
• License: http://creativecommons.org/licenses/by-nc-sa/4.0/
• Abstract: Field-programmable gate arrays (FPGAs) enable efficient neural-network inference, but most deployment flows either accelerate multiply-accumulate operations or convert pretrained quantized models into lookup tables (LUTs). We present DiffLUT-Net, an FPGA-native network connected by six-input LUTs that are trained from scratch. We jointly learn the 64 truth-table entries of a LUT and the source to each of its six input ports using a differentiable LUT function relaxation and hardware source selection. After training, the truth tables and connections are discretized, unused logic can be pruned, and the network is exported directly as synthesizable Verilog. Across five benchmarks, DiffLUT-Net achieves favorable accuracy-resource trade-offs. These results demonstrate the effectiveness of jointly learning LUT functions and sparse connectivity for compact FPGA-native inference. The code is available at https://github.com/TUDa-HWAI/DiffLUT-Network.

Related papers

• HGQ-LUT: Fast LUT-Aware Training and Efficient Architectures for DNN Inference [12.364180908244188]
  This work presents HGQ-LUT, a new LAT approach that achieves state-of-the-art hardware efficiency while accelerating training by over 100 times on modern GPUs.<n>By combining LUT-Dense and LUT-Conv layers, HGQ-LUT enables the automatic exploration of accuracy-resource trade-offs without manual bit-width tuning.<n>We further integrate HGQ-LUT into open-source toolchains, enabling unified design, compilation, and bit-exact verification of hybrid architectures.
  arXiv  Detail & Related papers  (2026-04-24T07:13:30Z)
• TorchLean: Formalizing Neural Networks in Lean [71.68907600404513]
  We introduce TorchLean, a framework that treats learned models as first-class mathematical objects with a single, precise semantics shared by execution and verification.<n>We validate TorchLean end-to-end on certified robustness, physics-informed residual bounds for PINNs, and Lyapunov-style neural controller verification.
  arXiv  Detail & Related papers  (2026-02-26T05:11:44Z)
• BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks [28.844098517315228]
  BitLogic is an end-to-end trainable framework for FPGA-native neural networks.<n>It replaces multiply-accumulate operations with differentiable LUT nodes that map directly to FPGA primitives.<n>It provides native binary computation, sparse connectivity, and efficient hardware realization.
  arXiv  Detail & Related papers  (2026-02-07T06:32:44Z)
• SparseLUT: Sparse Connectivity Optimization for Lookup Table-based Deep Neural Networks [0.0]
  This paper introduces SparseLUT, a connectivity-centric training technique tailored for LUT-based deep neural networks (DNNs)<n> Experimental results show consistent accuracy improvements across benchmarks, including up to a 2.13% increase on MNIST.<n>This is done without any hardware overhead and achieves state-of-the-art results for LUT-based DNNs.
  arXiv  Detail & Related papers  (2025-03-17T05:21:54Z)
• NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions [2.7086888205833968]
  Field-Programmable Gate Array (FPGA) accelerators have proven successful in handling latency- and resource-critical deep neural network (DNN) inference tasks. We propose relaxing the boundaries of neurons and mapping entire sub-networks to a single LUT. We validate our proposed method on a known latency-critical task, jet substructure tagging, and on the classical computer vision task, digit classification using MNIST.
  arXiv  Detail & Related papers  (2024-02-29T16:10:21Z)
• T-GAE: Transferable Graph Autoencoder for Network Alignment [79.89704126746204]
  T-GAE is a graph autoencoder framework that leverages transferability and stability of GNNs to achieve efficient network alignment without retraining. Our experiments demonstrate that T-GAE outperforms the state-of-the-art optimization method and the best GNN approach by up to 38.7% and 50.8%, respectively.
  arXiv  Detail & Related papers  (2023-10-05T02:58:29Z)
• FPGA-based AI Smart NICs for Scalable Distributed AI Training Systems [62.20308752994373]
  We propose a new smart network interface card (NIC) for distributed AI training systems using field-programmable gate arrays (FPGAs) Our proposed FPGA-based AI smart NIC enhances overall training performance by 1.6x at 6 nodes, with an estimated 2.5x performance improvement at 32 nodes, compared to the baseline system using conventional NICs.
  arXiv  Detail & Related papers  (2022-04-22T21:57:00Z)
• Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference [3.2296078260106174]
  We propose the learned optimization of such LUT-based topologies, resulting in higher-efficiency designs. Existing implementations of this class of architecture require the manual specification of the number of inputs per LUT, K. We propose logic shrinkage, a fine-grained netlist pruning methodology enabling K to be automatically learned for every LUT in a neural network targeted for FPGA inference.
  arXiv  Detail & Related papers  (2021-12-04T14:23:24Z)
• DS-Net++: Dynamic Weight Slicing for Efficient Inference in CNNs and Transformers [105.74546828182834]
  We show a hardware-efficient dynamic inference regime, named dynamic weight slicing, which adaptively slice a part of network parameters for inputs with diverse difficulty levels. We present dynamic slimmable network (DS-Net) and dynamic slice-able network (DS-Net++) by input-dependently adjusting filter numbers of CNNs and multiple dimensions in both CNNs and transformers.
  arXiv  Detail & Related papers  (2021-09-21T09:57:21Z)
• ShiftAddNet: A Hardware-Inspired Deep Network [62.88246517699367]
  ShiftAddNet is an energy-efficient multiplication-less deep neural network.<n>It leads to both energy-efficient inference and training, without compromising expressive capacity.<n> ShiftAddNet aggressively reduces over 80% hardware-quantified energy cost of DNNs training and inference, while offering comparable or better accuracies.
  arXiv  Detail & Related papers  (2020-10-24T05:09:14Z)
• ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks [63.91384986073851]
  We propose the autoencoder-based low-rank filter-sharing technique technique (ALF) ALF shows a reduction of 70% in network parameters, 61% in operations and 41% in execution time, with minimal loss in accuracy.
  arXiv  Detail & Related papers  (2020-07-27T09:01:22Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.