PATO: Producibility-Aware Topology Optimization using Deep Learning for
Metal Additive Manufacturing
- URL: http://arxiv.org/abs/2112.04552v1
- Date: Wed, 8 Dec 2021 19:52:24 GMT
- Title: PATO: Producibility-Aware Topology Optimization using Deep Learning for
Metal Additive Manufacturing
- Authors: Naresh S. Iyer, Amir M. Mirzendehdel, Sathyanarayanan Raghavan, Yang
Jiao, Erva Ulu, Morad Behandish, Saigopal Nelaturi, Dean M. Robinson
- Abstract summary: We propose PATO-a producibility-aware topology optimization (TO) framework to help efficiently explore the design space of components fabricated using metal additive manufacturing (AM)
We leverage the current advances in deep convolutional neural networks and present a high-fidelity surrogate model based on an Attention-based U-Net architecture to predict the maximum shear strain index (MSSI)
We demonstrate the effectiveness of the proposed method through benchmark studies in 3D as well as experimental validation.
- Score: 2.57172274875712
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: In this paper, we propose PATO-a producibility-aware topology optimization
(TO) framework to help efficiently explore the design space of components
fabricated using metal additive manufacturing (AM), while ensuring
manufacturability with respect to cracking. Specifically, parts fabricated
through Laser Powder Bed Fusion are prone to defects such as warpage or
cracking due to high residual stress values generated from the steep thermal
gradients produced during the build process. Maturing the design for such parts
and planning their fabrication can span months to years, often involving
multiple handoffs between design and manufacturing engineers. PATO is based on
the a priori discovery of crack-free designs, so that the optimized part can be
built defect-free at the outset. To ensure that the design is crack free during
optimization, producibility is explicitly encoded within the standard
formulation of TO, using a crack index. Multiple crack indices are explored and
using experimental validation, maximum shear strain index (MSSI) is shown to be
an accurate crack index. Simulating the build process is a coupled,
multi-physics computation and incorporating it in the TO loop can be
computationally prohibitive. We leverage the current advances in deep
convolutional neural networks and present a high-fidelity surrogate model based
on an Attention-based U-Net architecture to predict the MSSI values as a
spatially varying field over the part's domain. Further, we employ automatic
differentiation to directly compute the gradient of maximum MSSI with respect
to the input design variables and augment it with the performance-based
sensitivity field to optimize the design while considering the trade-off
between weight, manufacturability, and functionality. We demonstrate the
effectiveness of the proposed method through benchmark studies in 3D as well as
experimental validation.
Related papers
- Scalable AI Framework for Defect Detection in Metal Additive Manufacturing [2.303463009749888]
We leverage convolutional neural networks (CNN) to analyze thermal images of printed layers, automatically identifying anomalies that impact these properties.
Our work integrates these models in the CLoud ADditive MAnufacturing (CLADMA) module to enhance their accessibility and practicality for AM applications.
arXiv Detail & Related papers (2024-11-01T18:17:59Z) - Machine Learning Based Optimal Design of Fibrillar Adhesives [41.94295877935867]
Fibrillar adhesion, observed in animals like beetles, spiders, and geckos, relies on nanoscopic or microscopic fibrils to enhance surface adhesion via 'contact splitting'
Recent studies suggest that functional grading of fibril properties can improve adhesion, but this is a complex design challenge that has only been explored in simplified geometries.
We propose an ML-based tool that optimize the distribution of fibril compliance to maximize adhesive strength.
arXiv Detail & Related papers (2024-09-09T09:26:48Z) - Benchmarking End-To-End Performance of AI-Based Chip Placement Algorithms [77.71341200638416]
ChiPBench is a benchmark designed to evaluate the effectiveness of AI-based chip placement algorithms.
We have gathered 20 circuits from various domains (e.g., CPU, GPU, and microcontrollers) for evaluation.
Results show that even if intermediate metric of a single-point algorithm is dominant, the final PPA results are unsatisfactory.
arXiv Detail & Related papers (2024-07-03T03:29:23Z) - Deep Neural Operator Enabled Digital Twin Modeling for Additive Manufacturing [9.639126204112937]
A digital twin (DT) behaves as a virtual twin of the real-world physical process.
We present a deep neural operator enabled computational framework of the DT for closed-loop feedback control of the L-PBF process.
The developed DT is envisioned to guide the AM process and facilitate high-quality manufacturing.
arXiv Detail & Related papers (2024-05-13T03:53:46Z) - Mechanistic Design and Scaling of Hybrid Architectures [114.3129802943915]
We identify and test new hybrid architectures constructed from a variety of computational primitives.
We experimentally validate the resulting architectures via an extensive compute-optimal and a new state-optimal scaling law analysis.
We find MAD synthetics to correlate with compute-optimal perplexity, enabling accurate evaluation of new architectures.
arXiv Detail & Related papers (2024-03-26T16:33:12Z) - End-to-End Meta-Bayesian Optimisation with Transformer Neural Processes [52.818579746354665]
This paper proposes the first end-to-end differentiable meta-BO framework that generalises neural processes to learn acquisition functions via transformer architectures.
We enable this end-to-end framework with reinforcement learning (RL) to tackle the lack of labelled acquisition data.
arXiv Detail & Related papers (2023-05-25T10:58:46Z) - HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer
Compression [69.36555801766762]
We propose a hardware-aware tensor decomposition framework, dubbed HEAT, that enables efficient exploration of the exponential space of possible decompositions.
We experimentally show that our hardware-aware factorized BERT variants reduce the energy-delay product by 5.7x with less than 1.1% accuracy loss.
arXiv Detail & Related papers (2022-11-30T05:31:45Z) - Efficient Micro-Structured Weight Unification and Pruning for Neural
Network Compression [56.83861738731913]
Deep Neural Network (DNN) models are essential for practical applications, especially for resource limited devices.
Previous unstructured or structured weight pruning methods can hardly truly accelerate inference.
We propose a generalized weight unification framework at a hardware compatible micro-structured level to achieve high amount of compression and acceleration.
arXiv Detail & Related papers (2021-06-15T17:22:59Z) - An even-load-distribution design for composite bolted joints using a
novel circuit model and artificial neural networks [1.8472148461613158]
We propose a machine learning-based framework as an optimization method.
A novel circuit model is established to generate data samples for the training of artificial networks.
A database for all the possible inputs in the design space is built through the machine learning model.
arXiv Detail & Related papers (2021-05-15T10:10:47Z) - Offline Model-Based Optimization via Normalized Maximum Likelihood
Estimation [101.22379613810881]
We consider data-driven optimization problems where one must maximize a function given only queries at a fixed set of points.
This problem setting emerges in many domains where function evaluation is a complex and expensive process.
We propose a tractable approximation that allows us to scale our method to high-capacity neural network models.
arXiv Detail & Related papers (2021-02-16T06:04:27Z) - A Deep Learning Framework for Simulation and Defect Prediction Applied
in Microelectronics [3.8698051494433043]
We propose an architecture based on 3D Convolutional Neural Networks (3DCNN) in order to model the geometric variations in manufacturing parameters.
We validate our framework on a microelectronics use-case using the recently published PCB scans dataset.
arXiv Detail & Related papers (2020-02-25T15:54:33Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.