Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error
Mitigation
- URL: http://arxiv.org/abs/2201.12946v1
- Date: Mon, 31 Jan 2022 00:55:41 GMT
- Title: Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error
Mitigation
- Authors: Vedika Saravanan, Samah Mohamed Saeed
- Abstract summary: Noisy Intermediate-Scale Quantum (NISQ) algorithms should be carefully designed to boost the output state fidelity.
In the presence of spatial variation in the error rate of the quantum gates, adjusting the circuit structure can play a major role in mitigating errors.
We propose advanced predictive techniques to project the success rate of the circuit, and develop a new compilation phase post-quantum circuit mapping to improve its reliability.
- Score: 0.0
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: Noisy Intermediate-Scale Quantum (NISQ) algorithms, which run on noisy
quantum computers should be carefully designed to boost the output state
fidelity. While several compilation approaches have been proposed to minimize
circuit errors, they often omit the detailed circuit structure information that
does not affect the circuit depth or the gate count. In the presence of spatial
variation in the error rate of the quantum gates, adjusting the circuit
structure can play a major role in mitigating errors. In this paper, we exploit
the freedom of gate reordering based on the commutation rules to show the
impact of gate error propagation paths on the output state fidelity of the
quantum circuit, propose advanced predictive techniques to project the success
rate of the circuit, and develop a new compilation phase post-quantum circuit
mapping to improve its reliability. Our proposed approaches have been validated
using a variety of quantum circuits with different success metrics, which are
executed on IBM quantum computers. Our results show that rescheduling quantum
gates based on their error propagation paths can significantly improve the
fidelity of the quantum circuit in the presence of variable gate error rates.
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