Telecom wavelength quantum dots interfaced with silicon-nitride circuits via photonic wire bonding

• URL: http://arxiv.org/abs/2411.05647v1
• Date: Fri, 08 Nov 2024 15:39:59 GMT
• Title: Telecom wavelength quantum dots interfaced with silicon-nitride circuits via photonic wire bonding
• Authors: Ulrich Pfister, Daniel Wendland, Florian Hornung, Lena Engel, Hendrik Hüging, Elias Herzog, Ponraj Vijayan, Raphael Joos, Erik Jung, Michael Jetter, Simone L. Portalupi, Wolfram H. P. Pernice, Peter Michler,
• Abstract summary: In this work, 3D laser written photonic wire bonds are employed to interface triggered sources of quantum light. Single photons at telecom wavelengths are generated by the In(Ga)As quantum dots which are then funneled into a silicon-nitride chip.
• Score: 0.06521330875978466
• License:
• Abstract: Photonic integrated circuits find ubiquitous use in various technologies, from communication, to computing and sensing, and therefore play a crucial role in the quantum technology counterparts. Several systems are currently under investigation, each showing distinct advantages and drawbacks. For this reason, efforts are made to effectively combine different platforms in order to benefit from their respective strengths. In this work, 3D laser written photonic wire bonds are employed to interface triggered sources of quantum light, based on semiconductor quantum dots embedded into etched microlenses, with low-loss silicon-nitride photonics. Single photons at telecom wavelengths are generated by the In(Ga)As quantum dots which are then funneled into a silicon-nitride chip containing single-mode waveguides and beamsplitters. The second-order correlation function of g(2)(0) = 0.11+/-0.02, measured via the on-chip beamsplitter, clearly demonstrates the transfer of single photons into the silicon-nitride platform. The photonic wire bonds funnel on average 28.6+/-8.8% of the bare microlens emission (NA = 0.6) into the silicon-nitride-based photonic integrated circuit even at cryogenic temperatures. This opens the route for the effective future up-scaling of circuitry complexity based on the use of multiple different platforms.

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