Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

• URL: http://arxiv.org/abs/2412.00289v1
• Date: Fri, 29 Nov 2024 23:55:29 GMT
• Title: Controller-decoder system requirements derived by implementing Shor's algorithm with surface code
• Authors: Yaniv Kurman, Lior Ella, Nir Halay, Oded Wertheim, Yonatan Cohen,
• Abstract summary: Quantum Error Correction (QEC) is widely regarded as the most promising path towards quantum advantage. We show that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable through parallelizing decoding tasks. We also simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance, such as a physical error rate of 0.1% and 1000 qubits, are sufficient for the successful execution of the circuit.
• Score: 0.5592394503914488
• License:
• Abstract: Quantum Error Correction (QEC) is widely regarded as the most promising path towards quantum advantage, with significant advances in QEC codes, decoding algorithms, and physical implementations. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC, a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account all realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable through parallelizing decoding tasks and ensuring fast communication between decoders and the controller. Additionally, by extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance, such as a physical error rate of 0.1% and 1000 qubits, are sufficient for the successful execution of the circuit. These results are general to any non-Clifford QEC circuit of the same scale, providing a comprehensive overview of the classical components necessary for the experimental realization of non-Clifford circuits with QEC.

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