Roadmap to fault tolerant quantum computation using topological qubit arrays
- URL: http://arxiv.org/abs/2502.12252v1
- Date: Mon, 17 Feb 2025 19:00:10 GMT
- Title: Roadmap to fault tolerant quantum computation using topological qubit arrays
- Authors: David Aasen, Morteza Aghaee, Zulfi Alam, Mariusz Andrzejczuk, Andrey Antipov, Mikhail Astafev, Lukas Avilovas, Amin Barzegar, Bela Bauer, Jonathan Becker, Juan M. Bello-Rivas, Umesh Bhaskar, Alex Bocharov, Srini Boddapati, David Bohn, Jouri Bommer, Parsa Bonderson, Jan Borovsky, Leo Bourdet, Samuel Boutin, Tom Brown, Gary Campbell, Lucas Casparis, Srivatsa Chakravarthi, Rui Chao, Benjamin J. Chapman, Sohail Chatoor, Anna Wulff Christensen, Patrick Codd, William Cole, Paul Cooper, Fabiano Corsetti, Ajuan Cui, Wim van Dam, Tareq El Dandachi, Sahar Daraeizadeh, Adrian Dumitrascu, Andreas Ekefjärd, Saeed Fallahi, Luca Galletti, Geoff Gardner, Raghu Gatta, Haris Gavranovic, Michael Goulding, Deshan Govender, Flavio Griggio, Ruben Grigoryan, Sebastian Grijalva, Sergei Gronin, Jan Gukelberger, Jeongwan Haah, Marzie Hamdast, Esben Bork Hansen, Matthew Hastings, Sebastian Heedt, Samantha Ho, Justin Hogaboam, Laurens Holgaard, Kevin Van Hoogdalem, Jinnapat Indrapiromkul, Henrik Ingerslev, Lovro Ivancevic, Sarah Jablonski, Thomas Jensen, Jaspreet Jhoja, Jeffrey Jones, Kostya Kalashnikov, Ray Kallaher, Rachpon Kalra, Farhad Karimi, Torsten Karzig, Seth Kimes, Vadym Kliuchnikov, Maren Elisabeth Kloster, Christina Knapp, Derek Knee, Jonne Koski, Pasi Kostamo, Jamie Kuesel, Brad Lackey, Tom Laeven, Jeffrey Lai, Gijs de Lange, Thorvald Larsen, Jason Lee, Kyunghoon Lee, Grant Leum, Kongyi Li, Tyler Lindemann, Marijn Lucas, Roman Lutchyn, Morten Hannibal Madsen, Nash Madulid, Michael Manfra, Signe Brynold Markussen, Esteban Martinez, Marco Mattila, Jake Mattinson, Robert McNeil, Antonio Rodolph Mei, Ryan V. Mishmash, Gopakumar Mohandas, Christian Mollgaard, Michiel de Moor, Trevor Morgan, George Moussa, Anirudh Narla, Chetan Nayak, Jens Hedegaard Nielsen, William Hvidtfelt Padkær Nielsen, Frédéric Nolet, Mike Nystrom, Eoin O'Farrell, Keita Otani, Adam Paetznick, Camille Papon, Andres Paz, Karl Petersson, Luca Petit, Dima Pikulin, Diego Olivier Fernandez Pons, Sam Quinn, Mohana Rajpalke, Alejandro Alcaraz Ramirez, Katrine Rasmussen, David Razmadze, Ben Reichardt, Yuan Ren, Ken Reneris, Roy Riccomini, Ivan Sadovskyy, Lauri Sainiemi, Juan Carlos Estrada Saldaña, Irene Sanlorenzo, Simon Schaal, Emma Schmidgall, Cristina Sfiligoj, Marcus P. da Silva, Sarat Sinha, Mathias Soeken, Patrick Sohr, Tomas Stankevic, Lieuwe Stek, Patrick Strøm-Hansen, Eric Stuppard, Aarthi Sundaram, Henri Suominen, Judith Suter, Satoshi Suzuki, Krysta Svore, Sam Teicher, Nivetha Thiyagarajah, Raj Tholapi, Mason Thomas, Dennis Tom, Emily Toomey, Josh Tracy, Matthias Troyer, Michelle Turley, Matthew D. Turner, Shivendra Upadhyay, Ivan Urban, Alexander Vaschillo, Dmitrii Viazmitinov, Dominik Vogel, Zhenghan Wang, John Watson, Alex Webster, Joseph Weston, Timothy Williamson, Georg W. Winkler, David J. van Woerkom, Brian Paquelet Wütz, Chung Kai Yang, Richard Yu, Emrah Yucelen, Jesús Herranz Zamorano, Roland Zeisel, Guoji Zheng, Justin Zilke, Andrew Zimmerman,
- Abstract summary: We describe a device roadmap towards a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits.
Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; and an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits.
- Score: 37.024540100400536
- License:
- Abstract: We describe a concrete device roadmap towards a fault-tolerant quantum computing architecture based on noise-resilient, topologically protected Majorana-based qubits. Our roadmap encompasses four generations of devices: a single-qubit device that enables a measurement-based qubit benchmarking protocol; a two-qubit device that uses measurement-based braiding to perform single-qubit Clifford operations; an eight-qubit device that can be used to show an improvement of a two-qubit operation when performed on logical qubits rather than directly on physical qubits; and a topological qubit array supporting lattice surgery demonstrations on two logical qubits. Devices that enable this path require a superconductor-semiconductor heterostructure that supports a topological phase, quantum dots and coupling between those quantum dots that can create the appropriate loops for interferometric measurements, and a microwave readout system that can perform fast, low-error single-shot measurements. We describe the key design components of these qubit devices, along with the associated protocols for demonstrations of single-qubit benchmarking, Clifford gate execution, quantum error detection, and quantum error correction, which differ greatly from those in more conventional qubits. Finally, we comment on implications and advantages of this architecture for utility-scale quantum computation.
Related papers
- Near-Term Spin-Qubit Architecture Design via Multipartite Maximally-Entangled States [1.589509357008938]
We introduce four metrics which ascertain the quality of genuine multipartite quantum entanglement, along with circuit-level fidelity measures.
We devise simulations which combine expected hardware characteristics of spin-qubit devices with appropriate compilation techniques.
We find that sparsely-connected spin-qubit lattices can approach comparable values of our metrics to those of the most highly-connected device architecture.
arXiv Detail & Related papers (2024-12-17T12:55:40Z) - Towards early fault tolerance on a 2$\times$N array of qubits equipped with shuttling [0.0]
Two-dimensional grid of locally-interacting qubits is promising platform for fault tolerant quantum computing.
In this paper, we show that such constrained architectures can also support fault tolerance.
We demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform.
arXiv Detail & Related papers (2024-02-19T23:31:55Z) - Characterizing crosstalk of superconducting transmon processors [0.0]
We show how to efficiently and systematically characterize the magnitude of crosstalk effects on an entire quantum chip.
We propose more accurate means to simulate noisy quantum hardware by devising an appropriate crosstalk-aware noise model.
arXiv Detail & Related papers (2023-03-24T16:11:28Z) - Two qubits in one transmon -- QEC without ancilla hardware [68.8204255655161]
We show that it is theoretically possible to use higher energy levels for storing and controlling two qubits within a superconducting transmon.
The additional qubits could be used in algorithms which need many short-living qubits in error correction or by embedding effecitve higher connectivity in qubit networks.
arXiv Detail & Related papers (2023-02-28T16:18:00Z) - Graph test of controllability in qubit arrays: A systematic way to
determine the minimum number of external controls [62.997667081978825]
We show how to leverage an alternative approach, based on a graph representation of the Hamiltonian, to determine controllability of arrays of coupled qubits.
We find that the number of controls can be reduced from five to one for complex qubit-qubit couplings.
arXiv Detail & Related papers (2022-12-09T12:59:44Z) - Compact quantum kernel-based binary classifier [2.0684234025249717]
We present the simplest quantum circuit for constructing a kernel-based binary classifier.
The number of qubits is reduced by two and the number of steps is reduced linearly.
Our design also provides a straightforward way to handle an imbalanced data set.
arXiv Detail & Related papers (2022-02-04T14:30:53Z) - Measuring NISQ Gate-Based Qubit Stability Using a 1+1 Field Theory and
Cycle Benchmarking [50.8020641352841]
We study coherent errors on a quantum hardware platform using a transverse field Ising model Hamiltonian as a sample user application.
We identify inter-day and intra-day qubit calibration drift and the impacts of quantum circuit placement on groups of qubits in different physical locations on the processor.
This paper also discusses how these measurements can provide a better understanding of these types of errors and how they may improve efforts to validate the accuracy of quantum computations.
arXiv Detail & Related papers (2022-01-08T23:12:55Z) - Dual Map Framework for Noise Characterization of Quantum Computers [11.659279774157255]
We present a method that reconstructs a marginal (local) approximation of the effective noise (MATEN) channel, that acts as a single layer at the end of the circuit.
We demonstrate the performance of the method on Rigetti's Aspen-9 quantum computer for QAOA circuits up to six qubits.
arXiv Detail & Related papers (2021-12-08T17:00:51Z) - Fault-tolerant parity readout on a shuttling-based trapped-ion quantum
computer [64.47265213752996]
We experimentally demonstrate a fault-tolerant weight-4 parity check measurement scheme.
We achieve a flag-conditioned parity measurement single-shot fidelity of 93.2(2)%.
The scheme is an essential building block in a broad class of stabilizer quantum error correction protocols.
arXiv Detail & Related papers (2021-07-13T20:08:04Z) - Deterministic correction of qubit loss [48.43720700248091]
Loss of qubits poses one of the fundamental obstacles towards large-scale and fault-tolerant quantum information processors.
We experimentally demonstrate the implementation of a full cycle of qubit loss detection and correction on a minimal instance of a topological surface code.
arXiv Detail & Related papers (2020-02-21T19:48:53Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.