Scalable and Site-Specific Frequency Tuning of Two-Level System Defects in Superconducting Qubit Arrays

• URL: http://arxiv.org/abs/2503.04702v1
• Date: Thu, 06 Mar 2025 18:49:46 GMT
• Title: Scalable and Site-Specific Frequency Tuning of Two-Level System Defects in Superconducting Qubit Arrays
• Authors: Larry Chen, Kan-Heng Lee, Chuan-Hong Liu, Brian Marinelli, Ravi K. Naik, Ziqi Kang, Noah Goss, Hyunseong Kim, David I. Santiago, Irfan Siddiqi,
• Abstract summary: We introduce a scalable architecture for site-specific and in-situ manipulation of quantum two-level system defects.<n>Our method is resource efficient, combining TLS frequency tuning and universal single qubit control into a single on-chip control line per qubit.<n>We demonstrate a $36%$ improvement in average single qubit error rates and a $17%$ improvement in average energy relaxation times.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: State-of-the-art superconducting quantum processors containing tens to hundreds of qubits have demonstrated the building blocks for realizing fault-tolerant quantum computation. Nonetheless, a fundamental barrier to scaling further is the prevalence of fluctuating quantum two-level system (TLS) defects that can couple resonantly to qubits, causing excess decoherence and enhanced gate errors. Here we introduce a scalable architecture for site-specific and in-situ manipulation of TLS frequencies out of the spectral vicinity of our qubits. Our method is resource efficient, combining TLS frequency tuning and universal single qubit control into a single on-chip control line per qubit. We independently control each qubit's dissipative environment to dynamically improve both qubit coherence times and single qubit gate fidelities -- with a constant time overhead that does not scale with the device size. Over a period of 40 hours across 6 qubits, we demonstrate a $36\%$ improvement in average single qubit error rates and a $17\%$ improvement in average energy relaxation times. Critically, we realize a 4-fold suppression in the occurrence of TLS-induced performance outliers, and a complete reduction of simultaneous outlier events. These results mark a significant step toward overcoming the challenges that TLS defects pose to scaling superconducting quantum processors.

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