Characterising the failure mechanisms of error-corrected quantum logic gates

• URL: http://arxiv.org/abs/2504.07258v1
• Date: Wed, 09 Apr 2025 20:29:47 GMT
• Title: Characterising the failure mechanisms of error-corrected quantum logic gates
• Authors: Robin Harper, Constance Lainé, Evan Hockings, Campbell McLauchlan, Georgia M. Nixon, Benjamin J. Brown, Stephen D. Bartlett,
• Abstract summary: We use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic.<n>We identify that idling errors occurring during readout periods are highly detrimental to a quantum memory.<n>By varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates.
• Score: 2.5128687379089687
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: Mid-circuit measurements used in quantum error correction are essential in quantum computer architecture, as they read out syndrome data and drive logic gates. Here, we use a heavy-hex code prepared on a superconducting qubit array to investigate how different noise sources impact error-corrected logic. First, we identify that idling errors occurring during readout periods are highly detrimental to a quantum memory. We demonstrate significant improvements to the memory by designing and implementing a low-depth syndrome extraction circuit. Second, we perform a stability experiment to investigate the type of failures that can occur during logic gates due to readout assignment errors. We find that the error rate of the stability experiment improves with additional stabilizer readout cycles, revealing a trade-off as additional stability comes at the expense of time over which the memory can decay. We corroborate our results using holistic device benchmarking and by comparison to numerical simulations. Finally, by varying different parameters in our simulations we identify the key noise sources that impact the fidelity of fault-tolerant logic gates, with measurement noise playing a dominant role in logical gate performance.

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