Realization of Thread Level Parallelism on Quantum Devices

• URL: http://arxiv.org/abs/2511.05436v1
• Date: Fri, 07 Nov 2025 17:12:41 GMT
• Title: Realization of Thread Level Parallelism on Quantum Devices
• Authors: Keren Li, Zidong Lin, Zheng An, Guanru Feng, Zipeng Wu, Shiyao Hou, Jingen Xiang,
• Abstract summary: We introduce a classical linkage scheme that merges multiple independent quantum processing units (QPUs) into a single logical device.<n>We validate this architecture on clusters comprising up to sixteen benchtop nuclear magnetic resonance (NMR) quantum nodes.<n>Our results demonstrate that classical links suffice to scale up the logical size of quantum computations and realize general, non-unitary channels on today's hardware.
• Score: 0.052118759008482306
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Scaling up quantum devices is a central challenge for realizing practical quantum computation. Modular quantum architectures promise scalability, yet experiments to date have relied on either $\sim\!10^{3}$-qubit monolithic chips or fragile interconnects with high loss. Here, we introduce a classical linkage scheme that merges multiple independent quantum processing units (QPUs) into a single logical device, enabling thread-level parallelism (TLP). Theoretically, we show that quantum routines with product-state inputs and low-rank entangling layers can be re-expressed in an efficient parallelizable form. Experimentally, we validate this architecture on clusters comprising up to sixteen benchtop nuclear magnetic resonance (NMR) quantum nodes. A four-qubit Greenberger-Horne-Zeilinger (GHZ) state is partitioned into parallel two-qubit subcircuits, achieving a fidelity of $93.8\,\%$ with respect to the ideal state. A non-Hermitian evolution, implemented via a truncated Cauchy integral on Hermitian Hamiltonians, reproduces exact observables with high accuracy. Our results demonstrate that classical links suffice to scale up the logical size of quantum computations and realize general, non-unitary channels on today's hardware, opening an experimentally accessible route toward software-defined, clustered quantum accelerators.

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