Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid

• URL: http://arxiv.org/abs/2606.19482v1
• Date: Wed, 17 Jun 2026 18:14:23 GMT
• Title: Nearest-neighbour gates are all you need: High-rate quantum low-density parity-check codes on a planar grid
• Abstract summary: We introduce a family of quantum low-density parity-check codes, for the first time, using only nearest-neighbour gates on a square grid of qubits.<n>We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches.<n>These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits.
• Score: 3.6646002427839126
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: High-performance quantum low-density parity-check codes promise substantial reductions in the overhead of fault-tolerant quantum computation, but most constructions require long-range connectivity or qubit shuttling, both of which are difficult to realise in superconducting architectures. Here we introduce a family of quantum low-density parity-check codes that, for the first time, combines planar open-boundary layouts, finite-size advantages over surface codes, and syndrome extraction using only nearest-neighbour gates on a square grid of qubits. The key idea is to generate check-data connectivity dynamically: nearest-neighbour iSWAP walks both define the stabiliser supports and implement their measurement, avoiding the need for a long-range hardware graph. The resulting circuits achieve optimal constant-depth stabiliser measurement, independent of code size, and naturally remove leakage from the system by exchanging the role of check and data qubits at each syndrome extraction round. We find finite-size instances such as a [[323,14,15]] code, whose code-efficiency ratio is nearly an order of magnitude larger than that of rotated surface-code patches. At around 30 circuit qubits per logical qubit, the best directional tile-code layouts reduce the per-logical per-round logical error rate by up to a factor of 1000 relative to rotated surface-code memories. These results show that the advantages of quantum low-density parity-check codes can survive compilation into strictly planar nearest-neighbour circuits, bringing low-overhead fault-tolerant memories closer to near-term hardware.

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