A Unified Electrostatic-to-Spin Framework for Asymmetric Multi-Gate CMOS Quantum Devices

• URL: http://arxiv.org/abs/2607.04876v1
• Date: Mon, 06 Jul 2026 09:53:46 GMT
• Title: A Unified Electrostatic-to-Spin Framework for Asymmetric Multi-Gate CMOS Quantum Devices
• Abstract summary: Gate stacks in quantum chips are difficult to connect lithographic geometry, electrostatic confinement and many-electron spin filling in one transparent model.<n>Here we develop a reduced-order analytical framework for asymmetric multigate silicon quantum-dot devices.<n>The workflow therefore connects CMOS layout, device electrostatics, and potential-determined quantum observables, providing an auditable modelling layer for CMOS-based qubit design and DTCO.
• Score: 4.288703321880058
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: In advanced complementary metal-oxide-semiconductor (CMOS) quantum chips, compact gate stacks make it difficult to connect lithographic geometry, electrostatic confinement and many-electron spin filling in one transparent model. This connection is central to design-technology co-optimization (DTCO). Here we develop a reduced-order analytical framework for asymmetric multigate silicon quantum-dot devices. Its electrostatic core, the Poisson-kernel coupled-interface Green-function (PK-GF) model, agrees with an independent finite-volume solution at the millivolt scale for the matched two-dimensional problem, without fitting to that solution. We then pass the gate-derived confinement, rather than a harmonic or fitted potential, to a spin-valley many-body calculation for a jellybean quantum dot with N = 2-17 electrons at B = 5 T. The unrestricted Hartree-Fock (UHF) solution supports occupation-dependent, Wigner-molecule-like charge localization but likely overestimates spin polarization. Complete active-space configuration interaction (CASCI) supports a low-spin branch within the tested active spaces, which aligns with the experiments. The workflow therefore connects CMOS layout, device electrostatics, and potential-determined quantum observables, providing an auditable modelling layer for CMOS-based qubit design and DTCO.

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