Spin readout of a CMOS quantum dot by gate reflectometry and spin-dependent tunnelling

• URL: http://arxiv.org/abs/2005.07764v3
• Date: Fri, 12 Jun 2020 18:55:58 GMT
• Title: Spin readout of a CMOS quantum dot by gate reflectometry and spin-dependent tunnelling
• Authors: V. N. Ciriano-Tejel, M. A. Fogarty, S. Schaal, L. Hutin, B. Bertrand, Lisa Ibberson, M. F. Gonzalez-Zalba, J. Li, Y. -M. Niquet, M. Vinet and J. J. L. Morton
• Abstract summary: We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot fabricated using CMOS processes at the 300 mm wafer scale. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5-0.7 meV using excited state spectroscopy. These long lifetimes indicate the silicon nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Silicon spin qubits are promising candidates for realising large scale quantum processors, benefitting from a magnetically quiet host material and the prospects of leveraging the mature silicon device fabrication industry. We report the measurement of an electron spin in a singly-occupied gate-defined quantum dot, fabricated using CMOS compatible processes at the 300 mm wafer scale. For readout, we employ spin-dependent tunneling combined with a low-footprint single-lead quantum dot charge sensor, measured using radiofrequency gate reflectometry. We demonstrate spin readout in two devices using this technique, obtaining valley splittings in the range 0.5-0.7 meV using excited state spectroscopy, and measure a maximum electron spin relaxation time ($T_1$) of $9 \pm 3$ s at 1 Tesla. These long lifetimes indicate the silicon nanowire geometry and fabrication processes employed here show a great deal of promise for qubit devices, while the spin-readout method demonstrated here is well-suited to a variety of scalable architectures.

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