Related papers: Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits

Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits

URL: http://arxiv.org/abs/2312.14405v2
Date: Thu, 16 May 2024 10:53:52 GMT
Title: Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits
Authors: Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang,
Abstract summary: We propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices' information to learn the general rules of symmetric constraints.
Score: 15.126046083792597
License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
Abstract: In recent years, analog circuits have received extensive attention and are widely used in many emerging applications. The high demand for analog circuits necessitates shorter circuit design cycles. To achieve the desired performance and specifications, various geometrical symmetry constraints must be carefully considered during the analog layout process. However, the manual labeling of these constraints by experienced analog engineers is a laborious and time-consuming process. To handle the costly runtime issue, we propose a graph-based learning framework to automatically extract symmetric constraints in analog circuit layout. The proposed framework leverages the connection characteristics of circuits and the devices' information to learn the general rules of symmetric constraints, which effectively facilitates the extraction of device-level constraints on circuit netlists. The experimental results demonstrate that compared to state-of-the-art symmetric constraint detection approaches, our framework achieves higher accuracy and F1-score.

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