Logical multi-qubit entanglement with dual-rail superconducting qubits
- URL: http://arxiv.org/abs/2504.12099v1
- Date: Wed, 16 Apr 2025 14:02:30 GMT
- Title: Logical multi-qubit entanglement with dual-rail superconducting qubits
- Authors: Wenhui Huang, Xuandong Sun, Jiawei Zhang, Zechen Guo, Peisheng Huang, Yongqi Liang, Yiting Liu, Daxiong Sun, Zilin Wang, Yuzhe Xiong, Xiaohan Yang, Jiajian Zhang, Libo Zhang, Ji Chu, Weijie Guo, Ji Jiang, Song Liu, Jingjing Niu, Jiawei Qiu, Ziyu Tao, Yuxuan Zhou, Xiayu Linpeng, Youpeng Zhong, Dapeng Yu,
- Abstract summary: We demonstrate a superconducting processor integrating four dual-rail erasure qubits.<n>Each dual-rail qubit, encoded in pairs of tunable transmons, preserves millisecond-scale coherence times and single-qubit gate errors.<n>This work provides a blueprint ford quantum error correction with erasure qubits.
- Score: 14.808613294313902
- License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
- Abstract: Recent advances in quantum error correction (QEC) across hardware platforms have demonstrated operation near and beyond the fault-tolerance threshold, yet achieving exponential suppression of logical errors through code scaling remains a critical challenge. Erasure qubits, which enable hardware-level detection of dominant error types, offer a promising path toward resource-efficient QEC by exploiting error bias. Single erasure qubits with dual-rail encoding in superconducting cavities and transmons have demonstrated high coherence and low single-qubit gate errors with mid-circuit erasure detection, but the generation of multi-qubit entanglement--a fundamental requirement for quantum computation and error correction--has remained an outstanding milestone. Here, we demonstrate a superconducting processor integrating four dual-rail erasure qubits that achieves the logical multi-qubit entanglement with error-biased protection. Each dual-rail qubit, encoded in pairs of tunable transmons, preserves millisecond-scale coherence times and single-qubit gate errors at the level of $10^{-5}$. By engineering tunable couplings between logical qubits, we generate high-fidelity entangled states resilient to physical qubit noise, including logical Bell states (98.8% fidelity) and a three-logical-qubit Greenberger-Horne-Zeilinger (GHZ) state (93.5% fidelity). A universal gate set is realized through a calibrated logical controlled-NOT (CNOT) gate with 96.2% process fidelity, enabled by coupler-activated $XX$ interactions in the protected logical subspace. This work advances dual-rail architectures beyond single-qubit demonstrations, providing a blueprint for concatenated quantum error correction with erasure qubits.
Related papers
- Bias-preserving and error-detectable entangling operations in a superconducting dual-rail system [2.6938073024114755]
We design and realize a novel two-qubit gate for dual-rail erasure qubits based on superconducting microwave cavities.<n>The gate is high-speed ($sim$500 ns duration), and yields a residual gate infidelity after error detection below 0.1%.<n>We measure low erasure rates of $sim$0.5% per gate, as well as low and asymmetric dephasing errors that occur at least three times more frequently on control qubits.
arXiv Detail & Related papers (2025-03-13T22:49:43Z) - Erasure detection of a dual-rail qubit encoded in a double-post
superconducting cavity [1.8484713576684788]
We implement a dual-rail qubit encoded in a compact, double-post superconducting cavity.
We measure an erasure rate of 3.981 +/- 0.003 (ms)-1 and a residual dephasing error rate up to 0.17 (ms)-1 within the codespace.
arXiv Detail & Related papers (2023-11-08T01:36:51Z) - Fast Flux-Activated Leakage Reduction for Superconducting Quantum
Circuits [84.60542868688235]
leakage out of the computational subspace arising from the multi-level structure of qubit implementations.
We present a resource-efficient universal leakage reduction unit for superconducting qubits using parametric flux modulation.
We demonstrate that using the leakage reduction unit in repeated weight-two stabilizer measurements reduces the total number of detected errors in a scalable fashion.
arXiv Detail & Related papers (2023-09-13T16:21:32Z) - Demonstrating a long-coherence dual-rail erasure qubit using tunable transmons [59.63080344946083]
We show that a "dual-rail qubit" consisting of a pair of resonantly coupled transmons can form a highly coherent erasure qubit.
We demonstrate mid-circuit detection of erasure errors while introducing $ 0.1%$ dephasing error per check.
This work establishes transmon-based dual-rail qubits as an attractive building block for hardware-efficient quantum error correction.
arXiv Detail & Related papers (2023-07-17T18:00:01Z) - Dual-rail encoding with superconducting cavities [2.003418126964701]
We introduce the circuit-Quantum Electrodynamics (QED) dual-rail qubit in which our physical qubit is encoded in the single-photon subspace of two superconducting microwave cavities.
We describe how to perform a gate-based set of universal operations that includes state preparation, logical readout, and parametrizable single and two-qubit gates.
arXiv Detail & Related papers (2022-12-22T23:21:39Z) - Witnessing entanglement in trapped-ion quantum error correction under
realistic noise [41.94295877935867]
Quantum Error Correction (QEC) exploits redundancy by encoding logical information into multiple physical qubits.
We present a detailed microscopic error model to estimate the average gate infidelity of two-qubit light-shift gates used in trapped-ion platforms.
We then apply this realistic error model to quantify the multipartite entanglement generated by circuits that act as QEC building blocks.
arXiv Detail & Related papers (2022-12-14T20:00:36Z) - Universal qudit gate synthesis for transmons [44.22241766275732]
We design a superconducting qudit-based quantum processor.
We propose a universal gate set featuring a two-qudit cross-resonance entangling gate.
We numerically demonstrate the synthesis of $rm SU(16)$ gates for noisy quantum hardware.
arXiv Detail & Related papers (2022-12-08T18:59:53Z) - Erasure qubits: Overcoming the $T_1$ limit in superconducting circuits [105.54048699217668]
amplitude damping time, $T_phi$, has long stood as the major factor limiting quantum fidelity in superconducting circuits.
We propose a scheme for overcoming the conventional $T_phi$ limit on fidelity by designing qubits in a way that amplitude damping errors can be detected and converted into erasure errors.
arXiv Detail & Related papers (2022-08-10T17:39:21Z) - Software mitigation of coherent two-qubit gate errors [55.878249096379804]
Two-qubit gates are important components of quantum computing.
But unwanted interactions between qubits (so-called parasitic gates) can degrade the performance of quantum applications.
We present two software methods to mitigate parasitic two-qubit gate errors.
arXiv Detail & Related papers (2021-11-08T17:37:27Z) - Quantum Circuit Engineering for Correcting Coherent Noise [1.0965065178451106]
Crosstalk and several sources of operational interference are invisible when qubit or a gate is calibrated or benchmarked in isolation.
Unwanted Z-Z coupling on superconducting cross-resonance CNOT gates, is a commonly occurring unitary crosstalk noise.
Experiments aggressively deploy forced commutation of CNOT gates to obtain low noise state-preparation circuits.
arXiv Detail & Related papers (2021-09-08T10:33:18Z) - Fault-tolerant parity readout on a shuttling-based trapped-ion quantum
computer [64.47265213752996]
We experimentally demonstrate a fault-tolerant weight-4 parity check measurement scheme.
We achieve a flag-conditioned parity measurement single-shot fidelity of 93.2(2)%.
The scheme is an essential building block in a broad class of stabilizer quantum error correction protocols.
arXiv Detail & Related papers (2021-07-13T20:08:04Z) - Exponential suppression of bit or phase flip errors with repetitive
error correction [56.362599585843085]
State-of-the-art quantum platforms typically have physical error rates near $10-3$.
Quantum error correction (QEC) promises to bridge this divide by distributing quantum logical information across many physical qubits.
We implement 1D repetition codes embedded in a 2D grid of superconducting qubits which demonstrate exponential suppression of bit or phase-flip errors.
arXiv Detail & Related papers (2021-02-11T17:11:20Z) - Benchmarking Coherent Errors in Controlled-Phase Gates due to Spectator
Qubits [0.0]
We benchmark phase errors in a controlled-phase gate due to dispersive coupling of either of the qubits involved in the gate to one or more spectator qubits.
Our work is important for understanding limits to the fidelity of two-qubit gates with finite on/off ratio in multi-qubit settings.
arXiv Detail & Related papers (2020-05-12T16:44:27Z)
This list is automatically generated from the titles and abstracts of the papers in this site.
This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.