A fidelity-driven approach to quantum circuit partitioning via weighted hypergraphs for noise-resilient computation
- URL: http://arxiv.org/abs/2506.06867v2
- Date: Tue, 10 Jun 2025 16:17:11 GMT
- Title: A fidelity-driven approach to quantum circuit partitioning via weighted hypergraphs for noise-resilient computation
- Abstract summary: This paper introduces Fidelipart, a novel framework that transforms quantum circuits into a fidelity-aware hypergraph.<n>We evaluate Fidelipart against BQSKit's QuickPartitioner on 6-qubit/22-gate, 10-qubit/55-gate, and 24-qubit/88-gate benchmarks.<n>Results demonstrate Fidelipart's superior performance. It achieved SWAP gate reductions ranging from 77.3% to 100% and up to a 52.2% decrease in cut qubits.
- Score: 0.0
- License: http://creativecommons.org/licenses/by/4.0/
- Abstract: Effective circuit partitioning is critical for Noisy Intermediate-Scale Quantum (NISQ) devices, which are hampered by high error rates and limited qubit connectivity. Standard partitioning heuristics often neglect gate-specific error impacts, leading to suboptimal divisions with significant communication overhead and reduced fidelity. This paper introduces Fidelipart, a novel framework that transforms quantum circuits into a fidelity-aware hypergraph. In this model, gate error rates and structural dependencies inform the weights of nodes (gates) and hyperedges (representing multi-qubit interactions and qubit timelines), guiding an Mt-KaHyPar partitioner to minimize cuts through error-prone operations. We evaluated Fidelipart against BQSKit's QuickPartitioner on 6-qubit/22-gate, 10-qubit/55-gate, and 24-qubit/88-gate benchmarks under a linear topology with a consistent local contiguous re-mapping strategy. Results demonstrate Fidelipart's superior performance. It achieved SWAP gate reductions ranging from 77.3% to 100% and up to a 52.2% decrease in cut qubits. These physical improvements directly translated to estimated fidelity gains ranging from 27.3% to over 250%. While Fidelipart showed a modest runtime increase of 8-13% and variable effects on maximum partition depth, its substantial enhancement of circuit fidelity highlights the significant benefits of integrating detailed error-awareness into the partitioning process for more reliable NISQ computations.
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