Hybrid Cryptographic Monitoring System for Side-Channel Attack Detection on PYNQ SoCs

• URL: http://arxiv.org/abs/2508.21606v1
• Date: Fri, 29 Aug 2025 13:13:43 GMT
• Title: Hybrid Cryptographic Monitoring System for Side-Channel Attack Detection on PYNQ SoCs
• Authors: Nishant Chinnasami, Rasha Karakchi,
• Abstract summary: AES-128 encryption is theoretically secure but vulnerable in practical deployments due to timing and fault injection attacks on embedded systems.<n>This work presents a lightweight dual-detection framework combining statistical thresholding and machine learning (ML) for real-time anomaly detection.
• Score: 0.0
• License: http://creativecommons.org/licenses/by/4.0/
• Abstract: AES-128 encryption is theoretically secure but vulnerable in practical deployments due to timing and fault injection attacks on embedded systems. This work presents a lightweight dual-detection framework combining statistical thresholding and machine learning (ML) for real-time anomaly detection. By simulating anomalies via delays and ciphertext corruption, we collect timing and data features to evaluate two strategies: (1) a statistical threshold method based on execution time and (2) a Random Forest classifier trained on block-level anomalies. Implemented on CPU and FPGA (PYNQ-Z1), our results show that the ML approach outperforms static thresholds in accuracy, while maintaining real-time feasibility on embedded platforms. The framework operates without modifying AES internals or relying on hardware performance counters. This makes it especially suitable for low-power, resource-constrained systems where detection accuracy and computational efficiency must be balanced.

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