Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity

• URL: http://arxiv.org/abs/2201.02877v1
• Date: Sat, 8 Jan 2022 19:01:32 GMT
• Title: Compilation and scaling strategies for a silicon quantum processor with sparse two-dimensional connectivity
• Abstract summary: Inspired by the challenge of scaling up existing silicon quantum hardware, we propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes.
• Score: 0.0
• License: http://arxiv.org/licenses/nonexclusive-distrib/1.0/
• Abstract: Inspired by the challenge of scaling up existing silicon quantum hardware, we investigate compilation strategies for sparsely-connected 2d qubit arrangements and propose a spin-qubit architecture with minimal compilation overhead. Our architecture is based on silicon nanowire split-gate transistors which can form finite 1d chains of spin-qubits and allow the execution of two-qubit operations such as Swap gates among neighbors. Adding to this, we describe a novel silicon junction which can couple up to four nanowires into 2d arrangements via spin shuttling and Swap operations. Given these hardware elements, we propose a modular sparse 2d spin-qubit architecture with unit cells consisting of diagonally-oriented squares with nanowires along the edges and junctions on the corners. We show that this architecture allows for compilation strategies which outperform the best-in-class compilation strategy for 1d chains, not only asymptotically, but also down to the minimal structure of a single square. The proposed architecture exhibits favorable scaling properties which allow for balancing the trade-off between compilation overhead and co-location of classical control electronics within each square by adjusting the length of the nanowires. An appealing feature of the proposed architecture is its manufacturability using complementary-metal-oxide-semiconductor (CMOS) fabrication processes. Finally, we note that our compilation strategies, while being inspired by spin-qubits, are equally valid for any other quantum processor with sparse 2d connectivity.

Related papers

• A Scalable Distributed Quantum Optimization Framework via Factor Graph Paradigm [46.08923284345648]
  We introduce a structure-aware framework for distributed quantum optimization.<n>We find that for a search space of size $N$, our framework achieves $O(sqrtN)$ query complexity up to processors and separator dependent factors.<n>We show that structure-aware decomposition delivers a practical path to scalable distributed quantum optimization on quantum networks.
  arXiv  Detail & Related papers  (2026-03-08T15:15:52Z)
• A Folded Surface Code Architecture for 2D Quantum Hardware [5.881921610566565]
  Qubit shuttling has become an indispensable ingredient for scaling leading quantum computing platforms.<n>We present a scalable architecture that employs short-range shuttling to realize effective three-dimensional connectivity on a strictly two-dimensional device.<n>We show that this architecture reduces the runtime of all single-qubit logical Clifford gates and logical CNOTs within subsets of qubits from $mathcalO(d)$ in conventional surface code lattice surgery to constant time.
  arXiv  Detail & Related papers  (2026-01-27T17:29:16Z)
• Exploiting Movable Logical Qubits for Lattice Surgery Compilation [43.290156259065554]
  We introduce a paradigm shift by exploiting movable logical qubits via teleportation during the logical lattice surgery CNOT gate.<n> Numerical simulations show that the proposed approach can substantially reduce the routed circuit depth.<n>An open-source implementation of our method is available on GitHub.
  arXiv  Detail & Related papers  (2025-12-03T19:00:04Z)
• Scalable modular architecture for universal quantum computation [49.1574468325115]
  We show that it is sufficient to connect two qubit arrays that are evolution operator controllable by a single entangling two-qubit gate.<n>Our proof provides a template to build up modular QPUs from smaller building blocks with reduced numbers of local controls and couplings.
  arXiv  Detail & Related papers  (2025-07-19T16:45:47Z)
• Performance Characterization of a Multi-Module Quantum Processor with Static Inter-Chip Couplers [63.42120407991982]
  Three-dimensional integration technologies such as flip-chip bonding are a key prerequisite to realize large-scale superconducting quantum processors. We present a design for a multi-chip module comprising one carrier chip and four qubit modules. Measuring two of the qubits, we analyze the readout performance, finding a mean three-level state-assignment error of $9 times 10-3$ in 200 ns. We demonstrate a controlled-Z two-qubit gate in 100 ns with an error of $7 times 10-3$ extracted from interleaved randomized benchmarking.
  arXiv  Detail & Related papers  (2025-03-16T18:32:44Z)
• Quantum Compiling with Reinforcement Learning on a Superconducting Processor [55.135709564322624]
  We develop a reinforcement learning-based quantum compiler for a superconducting processor. We demonstrate its capability of discovering novel and hardware-amenable circuits with short lengths. Our study exemplifies the codesign of the software with hardware for efficient quantum compilation.
  arXiv  Detail & Related papers  (2024-06-18T01:49:48Z)
• Towards early fault tolerance on a 2$\times$N array of qubits equipped with shuttling [0.0]
  Two-dimensional grid of locally-interacting qubits is promising platform for fault tolerant quantum computing. In this paper, we show that such constrained architectures can also support fault tolerance. We demonstrate that error correction is possible and identify the classes of codes that are naturally suited to this platform.
  arXiv  Detail & Related papers  (2024-02-19T23:31:55Z)
• The SpinBus Architecture: Scaling Spin Qubits with Electron Shuttling [42.60602838972598]
  We introduce the SpinBus architecture, which uses electron shuttling to connect qubits and features low operating frequencies and enhanced qubit coherence. Control using room temperature instruments can plausibly support at least 144 qubits, but much larger numbers are conceivable with cryogenic control circuits.
  arXiv  Detail & Related papers  (2023-06-28T16:24:11Z)
• Quantum Gate Optimization for Rydberg Architectures in the Weak-Coupling Limit [55.05109484230879]
  We demonstrate machine learning assisted design of a two-qubit gate in a Rydberg tweezer system. We generate optimal pulse sequences that implement a CNOT gate with high fidelity. We show that local control of single qubit operations is sufficient for performing quantum computation on a large array of atoms.
  arXiv  Detail & Related papers  (2023-06-14T18:24:51Z)
• Pipeline quantum processor architecture for silicon spin qubits [0.0]
  Noisy intermediate-scale quantum (NISQ) devices seek to achieve quantum advantage over classical systems. We propose a NISQ processor architecture using a qubit pipeline' in which all run-time control is applied globally. This is achieved by progressing qubit states through a layered physical array of structures.
  arXiv  Detail & Related papers  (2023-06-13T10:35:01Z)
• Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors [5.012570785656963]
  Dynamically field-programmable qubit arrays (DPQA) have emerged as a promising platform for quantum information processing. In this paper, we consider a DPQA architecture that contains multiple arrays and supports 2D array movements. We show that our DPQA-based compiled circuits feature reduced scaling overhead compared to a grid fixed architecture.
  arXiv  Detail & Related papers  (2023-06-06T08:13:10Z)
• Mapping quantum circuits to modular architectures with QUBO [3.0148208709026005]
  In multi-core architectures, it is crucial to minimize the amount of communication between cores when executing an algorithm. We propose for the first time a Quadratic Unconstrained Binary Optimization technique to encode the problem and the solution. Our method showed promising results and performed exceptionally well with very dense and highly-parallelized circuits.
  arXiv  Detail & Related papers  (2023-05-11T09:45:47Z)
• Universal qudit gate synthesis for transmons [44.22241766275732]
  We design a superconducting qudit-based quantum processor. We propose a universal gate set featuring a two-qudit cross-resonance entangling gate. We numerically demonstrate the synthesis of $rm SU(16)$ gates for noisy quantum hardware.
  arXiv  Detail & Related papers  (2022-12-08T18:59:53Z)
• Synthesis of and compilation with time-optimal multi-qubit gates [0.46180371154032884]
  We develop a class of entangling multi-qubit gates for a quantum computing platform with fixed Ising-type interaction with all-to-all connectivity. We numerically demonstrate that the total multi-qubit gate time scales approximately linear in the number of qubits.
  arXiv  Detail & Related papers  (2022-06-13T18:00:04Z)
• A quantum processor based on coherent transport of entangled atom arrays [44.62475518267084]
  We show a quantum processor with dynamic, nonlocal connectivity, in which entangled qubits are coherently transported in a highly parallel manner. We use this architecture to realize programmable generation of entangled graph states such as cluster states and a 7-qubit Steane code state.
  arXiv  Detail & Related papers  (2021-12-07T19:00:00Z)
• Simulating nonnative cubic interactions on noisy quantum machines [65.38483184536494]
  We show that quantum processors can be programmed to efficiently simulate dynamics that are not native to the hardware. On noisy devices without error correction, we show that simulation results are significantly improved when the quantum program is compiled using modular gates.
  arXiv  Detail & Related papers  (2020-04-15T05:16:24Z)

This list is automatically generated from the titles and abstracts of the papers in this site.

This site does not guarantee the quality of this site (including all information) and is not responsible for any consequences.